Generally, a semiconductor package has a structure in which a semiconductor chip is covered with a resin portion.
For example, side surfaces and an active surface (circuit forming surface) of a semiconductor chip may be covered with a resin portion. And, a wiring structure in which a wiring layer electrically connected to the semiconductor chip and an insulating layer are stacked may be further formed on the resin portion.
For example, JP-2008-306071-A discloses a manufacturing method for such a semiconductor chip.
First, a supporting body is prepared. A semiconductor chip is mounted on the prepared supporting body such that a surface of the semiconductor chip, which is opposite to an active surface thereof, touches a surface of the supporting body. Then, the mounted semiconductor chip is sealed with a resin portion. Thereafter, a wiring layer and an insulating layer are stacked on the resin portion to form a wiring structure. Then, the supporting body is removed. Thus, a semiconductor package is manufactured.
In such manufacturing process, no warpage of the semiconductor package occurs and sufficient stiffness is provided, as long as a semiconductor chip is arranged on a supporting body. However, after the supporting body has been removed, warpage of a semiconductor package may be caused, and stiffness of the semiconductor package may become insufficient.
Since such warpage occurs due to thermal history obtained during a thermal treatment, e.g., solder reflowing, the amount of warpage may further increase during such thermal treatment.